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MESI protocol
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#	Item
21	The SGI Origin: A ccNUMA Highly Scalable Server James Laudon and Daniel Lenoski Silicon Graphics, IncNorth Shoreline Boulevard Mountain View, California 94043 Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 1999-02-05 11:20:29 Computer architecture Computer memory Parallel computing SGI Origin Non-Uniform Memory Access R10000 CPU cache Cell MESI protocol Computing Cache coherency Computer hardware
22	SH-X3 Flexible SuperH Multi-core for High-performance and Low-power Embedded Systems 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:59:21 Cache coherency Instruction set architectures Embedded microprocessors Microcontrollers SuperH MESI protocol CPU cache Central processing unit Bus sniffing Computer hardware Computing Computer architecture
23	, 82495DX/82490DX A HIGH PERFORMANCE 2ND LEVEL CACHE FOR THE Intel486™ DX CPU Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:46 Central processing unit Computer memory Computing Intel 80486 MESI protocol Intel 82497 Alpha 21164 Computer hardware CPU cache Cache
24	Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies∗ Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:45:45 CPU cache Dynamic random-access memory Memory refresh EDRAM Cache MESI protocol Random-access memory Memory hierarchy Computer data storage Computer memory Computer hardware Computing
25	Design Trade-Offs in High-Throughput Coherence Controllers Anthony-Trung Nguyen Microprocessor Research Labs Intel Corporation Santa Clara, CA[removed]removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-30 19:13:24 CPU cache Cache MESI protocol Parallel computing Computing Cache coherency Computer hardware
26	OmniOrder: Directory-Based Conflict Serialization of Transactions ∗ Xuehai Qian † University of California, Berkeley Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-04-19 12:44:14 Computer hardware Computer memory CPU cache MESI protocol MSI protocol Cache Transactional memory Parallel computing Cache coherency Computing Concurrent computing
27	BulkCommit: Scalable and Fast Commit of Atomic Blocks ∗ in a Lazy Multiprocessor Environment † Xuehai Qian , Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-10-25 19:56:50 Computer file formats Graphics file formats Cache coherency Chunk CPU cache MESI protocol ANIM Parallel computing C dynamic memory allocation Computing Computer memory Computer hardware
28	Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors∗ Karin Strauss Xiaowei Shen† Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-04-04 17:06:09 Cache coherency CPU cache Cache Central processing unit Computer memory MESI protocol Branch predictor Routing Snoop Dogg Computer architecture Computer hardware Computing
29	ISTITUTO EUROPEO DI DESIGN TARIFFARIO - CORSI MASTER IED Milano \| IED Roma \| IED Torino \| IED Firenze \| IED Venezia \| IED Cagliari Add to Reading List Source URL: www.academix.com.tr Language: English - Date: 2014-10-27 09:06:38 Istituto Europeo di Design MESI protocol
30	Memory Barriers: a Hardware View for Software Hackers Paul E. McKenney Linux Technology Center IBM Beaverton [removed] April 5, 2009 Add to Reading List Source URL: www.rdrop.com Language: English - Date: 2009-04-06 00:30:49 Computer architecture CPU cache MESI protocol Cache Central processing unit MSI protocol Write-once Computing Cache coherency Computer hardware